As is known to those skilled in the semiconductor art, transistors are the main building blocks of integrated circuits (ICs). Modem ICs interconnect millions of densely configured transistors that perform a wide variety of functions. To achieve this densely packed configuration, the physical dimensions of the transistors are typically scaled down to the sub-micron regime. Generally, the transistors used in the sub-micron regime typically include a polysilicon gate. However, polysilicon gates may suffer device performance degradation due to a polysilicon depletion effect in which an electric field applied to a polysilicon gate removes carriers (holes in a p-type doped polysilicon, or electrons in an n-type doped polysilicon) so as to create a depletion of carriers in the area of the polysilicon gate near the underlying gate dielectric of the transistor. This depletion effect results in a reduction in the strength of the electric field at the surface of the CMOS device when a voltage is applied to the polysilicon gate electrode, which can have an adverse affect on the transistor performance.
One proposed way of improving the performance of sub-micron transistors is to use metal gates in place of conventional polysilicon gates. While replacing traditional polysilicon gates with metal or metal alloy gate electrodes eliminates the polysilicon depletion effect, there are still problems associated with the use of such metal gates. Another way of improving the performance of a CMOS device is to include a conductive oxide as a contact layer. In such instances, the conductive oxide controls the threshold voltage of the CMOS device rather than the conductive metal used as the metal gate.
One problem encountered with metal gates is that the carriers from the metal gate can diffuse into the underlying gate dielectric material, thus causing shorting of the device.
In addition to using metal gates as a replacement for polysilicon gates, there is much research ongoing that deals with replacing conventional dielectrics such as silicon dioxide or silicon oxynitride with a gate dielectric that has a high dielectric constant. These materials are known in the art as “high k” materials with the term “high k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than 7.0.
CMOS technology can gain scaling advantages through the use of high k gate dielectrics with metal gates. These new components would replace the conventional polySi/SiO2 technology that is used today. However, difficulties have risen in implementing metal gate/high k technology, principally involving the threshold voltage (Vt) of the devices. This problem is particularly relevant in pFET devices.
CMOS processing inevitably requires high temperature (on the order of greater than 550° C.) steps to activate source/drain dopants, as well as reducing steps to passivate interfaces. It is commonly observed that after this processing, positive charge is induced in the dielectric that alters the threshold voltage of the device. The change in threshold voltage for a typical device gated with a p-type metal (with a workfunction near 5 eV) is 300-700 mV. In other words, the effective workfunction of the metal has moved from the silicon valence band to the middle of the silicon band gap. This would render a CMOS circuit including such a pFET device inoperable. During the high temperature processing, oxygen deficiencies have been created in the metal oxide. Schaeffer et al. “Contributions of the effective work function of platinum on hafnium dioxide”, Applied Physics Letters, Vol. 85, No. 10, Sep. 6, 2004, pp.1826 discuss these as interfacial vacancies. The interfacial vacancies can also be referred to as charged defects. It is also possible that these charged defects are conventional bulk oxygen vacancies in the high k gate dielectric that are electrostatically attracted to the interface formed between the gate conductor and the gate dielectric.
In view of the above, there is a need for providing a method of fabricating CMOS structures including a gate stack comprising at least a high k gate dielectric from which the charged defects have been substantially removed from the gate stack.